Modern requirements for a computer system may require that a computer be utilized to run several operating environments, or operating systems, at once, a technique often referred to as logical partitioning. In a typical embodiment, a single logically partitioned computer can run a plurality of operating systems in a corresponding plurality of logical partitions. Each operating system resides in its own logical partition, with each logical partition allocated a part of a processor, an entire processor, or multiple processors from the computer. Additionally, a portion of the computer's memory is allocated to each logical partition. All of the logical partitions are under the control of a partition manager. The partition manager is typically a part of the system firmware and manages the allocation of resources to the operating systems and logical partitions.
Recent advancements in processor technology have led to the development of a multi-element architecture (MEA) for processors. One multi-element processor architecture is the Cell Broadband Engine Architecture (“Cell”) processor architecture, jointly developed by International Business Machines Corporation (“IBM”), Sony Computer Entertainment, and Toshiba. In a typical Cell processor, there is a general purpose Power Processing Element (“PPE”) core with modest performance that controls a plurality of specialized Synergistic Processor Elements (“SPEs,” collectively) with accelerated multimedia application capabilities, vector processing application capabilities, or other dedicated computation capabilities. The PPE and SPEs are typically connected by a specialized high bandwidth data bus, commonly referred to as an Element Interconnect Bus (“EIB”). Because of this architecture, a Cell processor typically runs with great efficiency when general tasks are handled by the GPPE and mathematically intense tasks are handled by SPEs. However, also because of the architecture, a Cell processor often presents a challenging architecture on which to develop and implement complex software applications.
In computers with at least one MEA processor, there may be a need to virtualize operations and run a plurality of operating systems in a corresponding plurality of logical partitions. Currently, logical partitioning technology does not account for processors like a MEA processor, which is a multi-core architecture having multiple logical units, including a general purpose processing element (“GPPE”) and one or more synergistic processing elements (“SPEs”). In a typical logically partitioned computer, the logical partitions receive a percentage of physical processor, or CPU, resources. A virtualization layer time slices the CPU resources. Typically, time-slicing in a computer with a single CPU will cause the virtualization layer to alternate which logical partition's code runs on the single CPU. In conventional logically partitioned computers with more CPUs, time-slicing may alternate multiple logical partitions across multiple CPUs.
However, current logical partition technology typically does not work efficiently with MEA processors. A MEA processor often needs to take advantage of the particular strengths of its GPPE resources and specialized SPE resources to maximize performance. In a MEA processor, SPEs are typically designed to work on only one task at a time. As such, the SPEs are not typically configured with prediction units, caches, or out of order execution units. Additionally, SPEs typically have to be “configured” by an associated GPPE to perform a task. Unlike other processor architectures for which all of the allocatable resources in a processor can be allocated and time-sliced in essentially the same manner, significant architectural differences exist between GPPEs and SPEs, and due the heterogeneous nature of these different types of computing resources from the standpoint of allocating the resources to particular logical partitions and time-slicing, partitioning algorithms that might work well for GPPEs often would not work as well for SPEs.
Two operating system level programming models have been proposed to attempt to address logical partitioning issues of computers with MEA processors. Utilizing a MultiSPE programming model, all SPE resources are placed in a pool and assigned tasks from job queues in such a way as the SPEs can be said to be “shared” between logical partitions. However, use of a MultiSPE programming model does not guarantee a specific amount of SPE time that each logical partition receives because different jobs take varying amounts of time. In addition, an attempt to assign priority to tasks in a MultiSPE programming model may lead to starvation of SPE resources for a logical partition allocated less resources. Subsequently, the inability to control resources typically interferes with quality and efficiency of the use of a logical partition on a computer with at least one MEA processor.
Another operating system level programming model proposed to attempt to address logical partitioning issues of computers with MEA processors is Kernel Management of the GPPE resources and the SPE resources. Utilizing a Kernel Management programming model, both GPPEs and SPEs are collectively assigned slices of time according to logical partition requirements. In this model an entire Cell processor is time sliced in much the same way as a conventional processor. Although the GPPE resources may be easily time-sliced, the SPE resources often suffer great inefficiencies when an attempt is made to time slice such resources. In a Kernel Management model, the SPE resources are typically suspended and resumed in much the same way as is done for time slicing in computers with conventional processors in conventional virtualization implementations. This results in a high overhead and loss of efficiency. Each SPE must first have its data cleared, then reloaded by their associated GPPE with the data it is to process. Additionally, when the computer is configured with more than one logical partition, there is contention for SPE resources for logical partitions allocated fewer resources. Subsequently, this method often interferes with quality and efficiency of the logical partition on a computer with at least one MEA processor.
Consequently, there remains a need for effective sharing between logical partitions of the resources on a computer that utilizes multi-element architecture processors.